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NXP Semiconductors /MIMXRT1021 /IOMUXC_GPR /GPR13

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Interpret as GPR13

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ARCACHE_USDHC_0)ARCACHE_USDHC 0 (AWCACHE_USDHC_0)AWCACHE_USDHC 0 (CACHE_ENET_0)CACHE_ENET 0 (CACHE_USB_0)CACHE_USB

ARCACHE_USDHC=ARCACHE_USDHC_0, CACHE_ENET=CACHE_ENET_0, AWCACHE_USDHC=AWCACHE_USDHC_0, CACHE_USB=CACHE_USB_0

Description

GPR13 General Purpose Register

Fields

ARCACHE_USDHC

uSDHC block cacheable attribute value of AXI read transactions

0 (ARCACHE_USDHC_0): Cacheable attribute is off for read transactions

1 (ARCACHE_USDHC_1): Cacheable attribute is on for read transactions
AWCACHE_USDHC

uSDHC block cacheable attribute value of AXI write transactions

0 (AWCACHE_USDHC_0): Cacheable attribute is off for write transactions

1 (AWCACHE_USDHC_1): Cacheable attribute is on for write transactions
CACHE_ENET

ENET block cacheable attribute value of AXI transactions

0 (CACHE_ENET_0): Cacheable attribute is off for read/write transactions

1 (CACHE_ENET_1): Cacheable attribute is on for read/write transactions
CACHE_USB

USB block cacheable attribute value of AXI transactions

0 (CACHE_USB_0): Cacheable attribute is off for read/write transactions

1 (CACHE_USB_1): Cacheable attribute is on for read/write transactions

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data